XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 73
XC68HC05P18A
Manufacturer Part Number
XC68HC05P18A
Description
HCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet
1.XC68HC05P18A.pdf
(130 pages)
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8.7 Timer Status Register
MC68HC05P18A
MOTOROLA
Address:
OLVL — Output Compare Output Level Select Bit
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts (see
remaining step is to read (or write) the register associated with the active
status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to, for example,
measure an elapsed time. If the proper precautions are not designed into
the application software, a timer interrupt flag (TOF) could
unintentionally be cleared if:
The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
Reset:
Read:
Write:
1. The TSR is read when bit 5 (TOF) is set.
2. The LSB of the free-running counter is read, but not for the
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
purpose of servicing the flag or interrupt.
$0013
Bit 7
ICF
U
Figure 8-11. Timer Status Register (TSR)
= Unimplemented
OCF
U
6
16-Bit Timer
TOF
U
5
4
0
0
U = Unaffected
3
0
0
Figure
2
0
0
Timer Status Register
8-11). The only
1
0
0
Technical Data
16-Bit Timer
Bit 0
0
0
73
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