XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 72

• Manufacturer Part Number: XC68HC05P18A
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

16-Bit Timer
8.6 Timer Control Register
Technical Data
72
Address:
The timer control (TCR) shown in
(TMRH, TMRL, ACRH, ACRL) registers are the only registers of the 16-
bit timer affected by reset. The output compare port (TCMP) is forced
low after reset and remains low until OLVL is set and a valid output
compare occurs.
ICIE — Input Capture Interrupt Enable Bit
OCIE — Output Comapre Interrupt Enable Bit
TOIE — Timer Overflow Interrupt Enable Bit
IEDG — Input Capture Edge Select Bit
Reset:
Read:
Write:
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge,
setting it selects the rising edge.
$0012
Bit 7
ICIE
0
Figure 8-10. Timer Control Register (TCR)
= Unimplemented
OCIE
6
0
16-Bit Timer
TOIE
5
0
Figure 8-10
4
0
0
U = Unaffected
3
0
0
and free-running counter
2
0
0
MC68HC05P18A
IEDG
U
1
MOTOROLA
OLVL
Bit 0
0