XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 78

• Manufacturer Part Number: XC68HC05P18A
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

Serial Input/Output Ports (SIOP)
9.3 SIOP Signal Format
9.3.1 Serial Clock (SCK)
Technical Data
78
7 6 5 4 3 2 1 0
REGISTER
CONTROL
$0A
GENERATOR
PH2 CLOCK
BAUD
RATE
application software, these actions could affect the transmitted or
received data.
The SIOP subsystem is software configurable for master or slave
operation. There are no external mode selection inputs available (for
example, slave select pin).
The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time the first bit of received data is
accepted at the SDI pin and the first bit of transmitted data is presented
at the SDO pin (see
rising edge of SCK, and the first bit of transmitted data is presented at
the SDO pin. The transfer is terminated upon the eighth rising edge of
SCK.
Figure 9-1. SIOP Block Diagram
7 6 5 4 3 2 1 0
REGISTER
STATUS
HCO5 INTERNAL BUS
Serial Input/Output Ports (SIOP)
$0B
Figure
7 6 5 4 3 2 1 0
REGISTER
SHIFT
8-BIT
$0C
9-2). Data is captured at the SDI pin on the
SPE
SDO
SDI
SCK
CONTROL
LOGIC
I/O
SDO/PB5
SDI/PB6
SCK/PB7
MC68HC05P18A
MOTOROLA