XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 69

• Manufacturer Part Number: XC68HC05P18A
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

MC68HC05P18A
MOTOROLA
counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.
The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in
1. Block interrupts by setting the I bit in the condition code register
2. Write the MSB of the output compare register pair (OCRH) to
3. Read the timer status register (TSR) to arm the output compare
4. Write the LSB of the output compare register pair (OCRL) to
5. Unblock interrupts by clearing the I bit in the CCR.
BE
9B
B6
B7
B6
BF
Figure 8-7. Output Compare Software Initialization Example
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(CCR).
inhibit further compares until the LSB is written.
flag (OCF).
enable the output compare function and to clear its flag and
interrupt.
XX
XX
16
13
17
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16-Bit Timer
LDA
LDX
LDA
STX
STA
SEI
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DATAH
DATAL
OCRH
OCRL
TSR
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BLOCK INTERRUPTS
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HI BYTE FOR COMPARE
LOW BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
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Figure
8-7.
Output Compare
Technical Data
16-Bit Timer
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