M37221 Mitsubishi, M37221 Datasheet - Page 21

• Manufacturer Part Number: M37221
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

(1) I
The I
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I
ES0 bit of the I
counter is reset by a write instruction to the I
When both the ES0 bit and the MST bit of the I
(address 00D9
the I
ter is always enabled regardless of the ES0 bit value.
Note: To write data into the I
(2) I
The I
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
Not used in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents
(SAD6 to SAD0 + RBW) of the I
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
Bit 0: Read/write bit (RBW)
Bits 1 to 7: Slave address (SAD0–SAD6)
2
2
2
C data shift register. Reading data from the I
2
2
2
C address register (address 00D8
C data shift register (S0 : address 00D7
C data shift register is in a write enable status only when the
C Data Shift Register
MST bit to “0” (slave mode), keep an interval of 8 machine
cycles or more.
C Address Register
16
2
C control register (address 00DA
) are “1,” the SCL is output by a write instruction to
2
C data shift register after setting the
2
C address register.
16
) consists of a 7-bit slave
2
C data shift register.
16
2
2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
C data shift regis-
16
C status register
) is an 8-bit shift
) is “1.” The bit
M37221EF-XXXSP,M37221EFSP
Fig. 15. Structure of I
(3) I
The I
control, SCL mode and SCL frequency.
These bits control the SCL frequency. Refer to Table 3.
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
This bit sets the SDA status when an ACK clock is generated. When
this bit is set to “0,” the ACK return mode is set and make SDA “L” at
the occurrence of an ACK clock. When the bit is set to “1,” the ACK
non-return mode is set. The SDA is held in the “H” status at the oc-
currence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made “L” (ACK is returned). If there is a mismatch between the slave
address and the address data, the SDA is automatically made
“H”(ACK is not returned).
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA “H”) and receives the ACK bit generated
by the data receiving device.
Note: Do not write data into the I
ACK clock: Clock for acknowledgement
Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
Bit 5: SCL mode specification bit (FAST MODE)
Bit 6: ACK bit (ACK BIT)
Bit 7: ACK clock bit (ACK)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
7
2
2
C clock control register (address 00DB
transmitting. If data is written during transmitting, the I
generator is reset, so that data cannot be transmitted nor-
mally.
C Clock Control Register
with ON-SCREEN DISPLAY CONTROLLER
2
C address register
2
C clock control register during
0
I
(S0D: address 00D8
2
Read/write bit
Slave address
C address register
16
) is used to set ACK
2
C clock
16
)
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