M37221 Mitsubishi, M37221 Datasheet - Page 27

• Manufacturer Part Number: M37221
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

When the first-byte address data matches the slave address, the
AAS bit of the I
the second-byte address data is stored into the I
(address 00D7
ond-byte data and the slave address by software. When the address
data of the 2nd byte matches the slave address, set the RBW bit of
the I
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I
sion format when the 10-bit addressing format is selected, refer to
Figure 24, (3) and (4).
(10) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
(11) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode and using
the addressing format is shown below.
Set a slave address in the high-order 7 bits of the I
register (address 00D8
Set the ACK return mode and SCL = 100 kHz by setting “85
the I
Set “10
the SCL at the “H” level.
Set a communication enable status by setting “48
control register (address 00DA
Set the address data of the destination of transmission in the high-
order 7 bits of the I
“0” in the least significant bit.
Set “F0
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I
At this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
Set “D0
if ACK is not returned or transmission ends, a STOP condition
occurs.
Set a slave address in the high-order 7 bits of the I
register (address 00D8
Set the no ACK clock mode and SCL = 400 kHz by setting “25
in the I
Set “10
the SCL at the “H” level.
Set a communication enable status by setting “48
control register (address 00DA
When a START condition is received, an address comparison is
made.
2
C address register (address 00D8
.
2
2
C address register (address 00D8
C clock control register (address 00DB
2
16
16
16
16
C clock control register (address 00DB
” in the I
” in the I
” in the I
” in the I
2
16
C status register (address 00D9
), make an address comparison between the sec-
2
2
2
2
2
C status register (address 00D9
C status register (address 00D9
C status register (address 00D9
C status register (address 00D9
C data shift register (address 00D7
16
16
2
) and “0” in the RBW bit.
) and “0” in the RBW bit.
C data shift register (address 00D7
16
16
).
).
16
16
) to “1” by software. This
). For the data transmis-
16
2
16
C data shift register
) is set to “1.” After
).
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
).
16
__
16
16
16
) to generate
16
16
2
2
). After this,
” in the I
” in the I
C address
16
C address
) and hold
) and hold
) and set
16
16
” in
16
2
2
C
C
).
”
M37221EF-XXXSP,M37221EFSP
•When all transmitted addresses are “0” (general call)
•When the transmitted addresses match the address set in
•In the cases other than the above
Set dummy data in the I
When receiving control data of more than 1 byte, repeat step
When a STOP condition is detected, the communication ends.
AD0 of the I
an interrupt request signal occurs.
AAS of the I
an interrupt request signal occurs.
AD0 and AAS of the I
set to “0” and no interrupt request signal occurs.
with ON-SCREEN DISPLAY CONTROLLER
2
2
C status register (address 00D9
C status register (address 00D9
2
2
C status register (address 00D9
C data shift register (address 00D7
16
16
) is set to “1” and
) is set to “1” and
16
) are
16
27
).
.