M37221 Mitsubishi, M37221 Datasheet - Page 22

• Manufacturer Part Number: M37221
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

Fig. 16. Structure of I
Table 3. Set values of I
Note: At 400 kHz in the high-speed clock mode, the duty is 40%.
22
CCR4
ACK
0
0
0
0
0
0
0
1
1
1
7
CCR3
Setting value of
ACK
In the other cases, the duty is 50%.
BIT
CCR4–CCR0
0
0
0
0
0
0
0
1
1
1
MODE
FAST
CCR2
0
0
0
0
1
1
1
1
1
1
CCR4 CCR3 CCR2 CCR1 CCR0
CCR1
0
0
1
1
0
0
1
0
1
1
2
C clock control register
CCR0
2
C clock control register and SCL frequency
0
1
0
1
0
1
0
1
0
1
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
500/CCR value
Standard clock
mode
(at
100
0
83.3
17.2
16.6
16.1
SCL frequency
= 4MHz, unit : kHz)
I
(S2 : address 00DB
SCL frequency
control bits
Refer to Table 3.
SCL mode
specification bit
ACK bit
ACK clock bit
2
0 : Standard clock
1 : High-speed clock
0 : ACK is returned.
1 : ACK is not returned.
0 : No ACK clock
1 : ACK clock
C clock control register
mode
mode
High-speed clock
1000/CCR value
Setting disabled
Setting disabled
Setting disabled
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
mode
333
250
166
400(Note)
34.5
33.3
32.3
16
)
M37221EF-XXXSP,M37221EFSP
(4) I
The I
tion format.
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “000
the address data is always transmitted and received in 8 bits.
This bit enables to use the multimaster I
bit is set to “0,” the use disable status is provided, so the SDA and
the SCL become high-impedance. When the bit is set to “1,” use of
the interface is enabled.
When ES0 = “0,” the following is performed.
•
•
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
eral call (refer to “(5) I
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I
dress 00D8
to “1,” the 10-bit addressing format is selected, all the bits of the I
address register are compared with address data.
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 17).
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I
status register at address 00D9
Writing data to the I
abled.
Bits 0 to 2: Bit counter (BC0–BC2)
Bit 3: I
Bit 4: Data format selection bit (ALS)
Bit 5: Addressing format selection bit (10BIT SAD)
Bits 6 and 7: Connection control bits between I
2
2
C control register (address 00DA
C Control Register
2
C interface use enable bit (ES0)
16
) are compared with address data. When this bit is set
and ports (BSEL0, BSEL1)
with ON-SCREEN DISPLAY CONTROLLER
2
2
MITSUBISHI MICROCOMPUTERS
C data shift register (address 00D7
C Status Register,” bit 1) is received, trans-
16
).
16
2
C BUS interface. When this
) controls data communica-
2
C address register (ad-
2
C-BUS interface
16
) is dis-
2
” and
2
2
C
C