M37221 Mitsubishi, M37221 Datasheet - Page 26

• Manufacturer Part Number: M37221
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

(8) START/STOP Condition Detecting Condi-
The START/STOP condition detecting conditions are shown in Fig-
ure 23 and Table 5. Only when the 3 conditions of Table 5 are satis-
fied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
Fig. 23. START condition/STOP condition detecting timing diagram
Table 5. START condition/STOP condition detecting conditions
Note: Absolute time at
Fig. 24. Address data communication format
26
6.5 s (26 cycles) <SCL release
3.25 s (13 cycles) < Setup time
3.25 s (13 cycles) < Hold time
(START condition)
(STOP condition)
tions
(MST = 0), an interrupt request signal “IICIRQ” occurs to the
CPU.
Standard clock mode
notes the number of cycles.
SCL
SDA
SDA
(2) A master-receiver receives data from a slave-transmitter
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
(1) A master-transmitter transmits data to a slave-receiver
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
S
S
S
Slave address R/W
Slave address R/W
Slave address
1st 7 bits
Slave address
1st 7 bits
time
7 bits
7 bits
7 bits
7 bits
= 4 MHz. The value in parentheses de-
Setup
Setup
time
time
SCL release time
1.0 s (4 cycles) <SCL release
0.5 s (2 cycles) < Setup time
0.5 s (2 cycles) < Hold time
R/W
R/W
“0”
“1”
“0”
“0”
High-speed clock mode
Hold time
Hold time
A
A
A
A
P : STOP condition
R/W : Read/Write bit
1 to 8 bits
1 to 8 bits
Slave address
2nd byte
Slave address
2nd byte
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Data
Data
time
8 bits
8 bits
A
A
1 to 8 bits
1 to 8 bits
A
A
Data
Data
1 to 8 bits
Sr
Data
M37221EF-XXXSP,M37221EFSP
(9) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
A/A
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I
00D8
the RBW bit of the I
made. For the data transmission format when the 7-bit addressing
format is selected, refer to Figure 24, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I
register (address 00D8
dress comparison between the RBW bit of the I
ter (address 00D8
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
A
2
2
C control register (address 00DA
C control register (address 00DA
Slave address
1st 7 bits
From master to slave
From slave to master
16
7 bits
P
P
A
). At the time of this comparison, address comparison of
1 to 8 bits
Data
with ON-SCREEN DISPLAY CONTROLLER
R/W
16
“1”
MITSUBISHI MICROCOMPUTERS
2
) and the R/W bit which is the last bit of the
C address register (address 00D8
A/A
16
1 to 8 bits
). At the time of this comparison, an ad-
Data
P
16
16
2
A
) to “0.” The first 7-bit address
C address register (address
) to “1.” An address compari-
1 to 8 bits
Data
2
C address regis-
A
2
C address
16
P
) is not