M37221 Mitsubishi, M37221 Datasheet - Page 23

• Manufacturer Part Number: M37221
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

Fig. 17. Connection port control by BSEL0 and BSEL1
(5) I
The I
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit
is set to “1.” Except in the ACK mode, the last bit value of received
data is input. The state of this bit is changed from “1” to “0” by execut-
ing a write instruction to the I
This bit is set to “1” when a general call whose address data is all “0”
is received in the slave mode. By a general call of the master device,
every slave device receives control data after the general call. The
AD0 bit is set to “0” by detecting the STOP condition or START con-
dition.
This flag indicates a comparison result of address data.
General call: The master transmits the general call address “00
Bit 0: Last receive bit (LRB)
Bit 1: General call detecting flag (AD0)
Bit 2: Slave address comparison flag (AAS)
In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
instruction to the I
•
•
•
The state of this bit is changed from “1” to “0” by executing a write
The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-order
7 bits of the I
A general call is received.
When the address data is compared with the I
register (8 bits consisted of slave address and RBW), the first
bytes agree.
2
2
C status register (address 00D9
C Status Register
Multi-master
I
interface
2
C-BUS
to all slaves.
SDA
SCL
2
C address register (address 00D8
2
C data shift register (address 00D7
2
C data shift register (address 00D7
16
) controls the I
“0”
“1” BSEL0
“0”
“1” BSEL1
“0”
“1” BSEL0
“0”
“1” BSEL1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
16
SDA1/P1
SDA2/P1
SCL1/P1
SCL2/P1
2
).
C-BUS inter-
2
C address
16
).
1
2
3
4
16
16
).
”
M37221EF-XXXSP,M37221EFSP
Fig. 18. Structure of I
BSEL1 BSEL0 10 BIT
7
SAD
with ON-SCREEN DISPLAY CONTROLLER
ALS ES0 BC2 BC1 BC0
2
C control register
0
I
(S1D : address 00DA
Bit counter (Number of
transmit/receive bits)
I
enable bit
Data format selection bit
Addressing format
selection bit
Connection control bits
between I
interface and ports
2
2
C control register
C-BUS interface use
b2 b1 b0
b7 b6 Connection port
0 : Addressing format
1 : Free data format
0 : 7-bit addressing
1 : 10-bit addressing
0
0
1
1
0
0
0
0
1
1
1
1
0 : Disabled
1 : Enabled
format
format
0
0
1
1
0
0
1
1
0 : None
1 : SCL1, SDA1
0 : SCL2, SDA2
1 : SCL1, SDA1,
2
0 : 8
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
C-BUS
SCL2, SDA2
16
23
)