M37221 Mitsubishi, M37221 Datasheet - Page 25

• Manufacturer Part Number: M37221
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

Fig. 20. Interrupt request signal generating timing
Fig. 19. Structure of I
MST
7
Note: These bit and flags can be read out but cannot
IICIRQ
SCL
TRX BB PIN AL AAS AD
PIN
be written.
2
C status register
0
LRB
0
I
(S1 : address 00D9
Last receive bit (Note)
General call detecting flag
(Note)
Arbitration lost detecting flag
(Note)
Communication mode
specification bits
Slave address comparison
flag (Note)
I
request bit
Bus busy flag
2
2
C status register
C-BUS interface interrupt
0 : Last bit = “0”
1 : Last bit = “1”
0 : No general call detected
1 : General call detected
0 : Not detected
1 : Detected
0 : Address disagreement
1 : Address agreement
0 : Interrupt request issued
1 : No interrupt request
0 : Bus free
1 : Bus busy
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
issued
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
16
)
M37221EF-XXXSP,M37221EFSP
(6) START Condition Generating Method
When the ES0 bit of the I
execute a write instruction to the I
for setting the MST, TRX and BB bits to “1.” Then a START condition
occurs. After that, the bit counter becomes “000
byte is output. The START condition generating timing and BB bit set
timing are different in the standard clock mode and the high-speed
clock mode. Refer to Figure 21, the START condition generating tim-
ing diagram, and Table 4, the START condition/STOP condition gen-
erating timing table.
Fig. 21. START condition generating timing diagram
(7) STOP Condition Generating Method
When the ES0 bit of the I
execute a write instruction to the I
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”.
Then a STOP condition occurs. The STOP condition generating tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 22, the STOP
condition generating timing diagram, and Table 4, the START condi-
tion/STOP condition generating timing table.
Fig. 22. STOP condition generating timing diagram
Table 4. START condition/STOP condition generating timing table
Note: Absolute time at
Setup time
Hold time
Set/reset time
for BB flag
SCL
SDA
BB flag
I
write signal
I
write signal
SCL
SDA
2
BB flag
Item
2
C status register
C status register
notes the number of cycles.
with ON-SCREEN DISPLAY CONTROLLER
Standard clock mode
5.0 s (20 cycles)
5.0 s (20 cycles)
3.0 s (12 cycles)
2
2
C control register (address 00DA
C control register (address 00DA
= 4 MHz. The value in parentheses de-
Setup
Setup
Setup
time
time
time
2
2
C status register (address 00D9
C status register (address 00D9
Reset time for
BB flag
Hold time
Set time for
BB flag
Hold time
High-speed clock mode
1.5 s (6 cycles)
2.5 s (10 cycles)
2.5 s (10 cycles)
2
” and an SCL for 1
16
16
) is “1,”
) is “1,”
16
16
25
)
)