GS8662S08E GSI [GSI Technology], GS8662S08E Datasheet - Page 12

• Manufacturer Part Number: GS8662S08E
• Description: 72Mb Burst of 2 DDR SigmaSIO-II SRAM
• Manufacturer: GSI [GSI Technology]

FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a
vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the
impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts
in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets
and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum
level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur
whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z.
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
Notes:
1.
2.
3.
4.
5.
6.
7.
K
(t
A
X
V
V
n
“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
“—” indicates that the input requirement or output state is determined by the next operation.
Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
CQ is never tristated.
Users should not clock in metastable addresses.
↑
)
K
(t
LD
1
0
0
n
↑
)
R/W
K
(t
X
1
0
n
↑
)
Operation
Current
Deselect
Read
Write
K
(t
n
↑
)
12/37
(t
K
n+1
D0
D
X
X
↑
GS8662S08/09/18/36E-333/300/250/200/167
)
(t
K
n+1
D1
—
—
D
↑
)
(t
K
Hi-Z
Hi-Z
n+1
Q0
Q
↑
)
© 2005, GSI Technology
Preliminary
(t
K
n+1
Q1
—
—
Q
↑
)
SS