GS8662S08E GSI [GSI Technology], GS8662S08E Datasheet - Page 8

• Manufacturer Part Number: GS8662S08E
• Description: 72Mb Burst of 2 DDR SigmaSIO-II SRAM
• Manufacturer: GSI [GSI Technology]

Power-Up Sequence for SigmaQuad-II SRAMs
SigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
V
V
V
V
V
DDQ
Doff
V
DDQ
Doff
REF
REF
DD
DD
K
K
K
K
Power-Up Sequence
DLL Constraints
Power UP Interval
Power UP Interval
1. Power-up and maintain Doff at low state.
2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.
3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.
Note:
If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become
stablized.
• The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t
• The DLL cannot operate at a frequency lower than 119 MHz.
• If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.
the initial stage.
1a.
1b. Apply V
1c.
Apply V
Apply V
DD
DDQ
REF
.
.
(may also be applied at the same time as V
Unstable Clocking Interval
Unstable Clocking Interval
Power-Up Sequence (Doff controlled)
Power-Up Sequence (Doff tied High)
8/37
DDQ
).
Stop Clock Interval
30ns Min
GS8662S08/09/18/36E-333/300/250/200/167
KCVar
DLL Locking Interval (1024 Cycles)
on page 21).
DLL Locking Interval (1024 Cycles)
© 2005, GSI Technology
Preliminary
Normal Operation
Normal Operation