GS8662S08E GSI [GSI Technology], GS8662S08E Datasheet - Page 31

• Manufacturer Part Number: GS8662S08E
• Description: 72Mb Burst of 2 DDR SigmaSIO-II SRAM
• Manufacturer: GSI [GSI Technology]

JTAG TAP Instruction Set Summary
JTAG Port Recommended Operating Conditions and DC Characteristics
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
Note:
The input level of SRAM pin is to follow the SRAM DC specification.
Instruction
SAMPLE-Z
PRELOAD
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
SAMPLE/
EXTEST
IDCODE
BYPASS
RFU
RFU
RFU
Output High Voltage (I
Output Low Voltage (I
Power Supply Voltage
Code
Input High Voltage
Input Low Voltage
000
001
010
011
100
101
110
111
Parameter
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Do not use this instruction; Reserved for Future Use.
Do not use this instruction; Reserved for Future Use.
Places Bypass Register between TDI and TDO.
OH
OL
= –2 mA)
= 2 mA)
31/37
Symbol
V
Description
V
V
V
V
DDQ
OH
OL
IH
IL
GS8662S08/09/18/36E-333/300/250/200/167
Min.
–0.3
V
1.7
1.3
1.4
SS
Typ.
1.8
—
—
—
—
V
© 2005, GSI Technology
DD
Max.
V
1.9
0.5
0.4
DD
+ 0.3
Preliminary
Unit
Notes
V
V
V
V
V
1, 2
1
1
1
1
1
1
1