SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 112
SCD1284
Manufacturer Part Number
SCD1284
Description
IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.SCD1284.pdf
(176 pages)
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CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.1.9
7.1.10
7.1.11
112
Register Name: RIR
Register Description: Receive Interrupt
Access: Read/Write
Register Name: SVRR
Register Description: Service Request
Access: Read only
Register Name: RICR
Register Description: Receive Interrupting Channel
Access: Read/Write
DMAREQ
RxIreq
Bit 7
Bit 7
X
7
Bit
7
6
5
4
3
Note: This value does not have any effect on baud rate generation.
The time period generated by this register drives the receive timer and activates the ‘no new data’
and ‘receive data timeout’ interrupts. See the receiver operation discussion in
description of receiver timer functions.
Receive Interrupting Channel Register
See
Receive Interrupt Register
See
Service Request Register
The SVRR reflects the inverse of the state of the service request pins (SVCREQR*, SVCREQT*,
and SVCREQM*). Its primary use is in polled systems, and it allows system software to determine
what, if any, service requests are pending.
DMA Request Status: ‘1’ indicates request pending.
ExtM: Reflects the current state of the external SVCREQM* signal.
ExtT: Reflects the current state of the external SVCREQT* signal.
ExtR: Reflects the current state of the external SVCREQR* signal.
Service Request Parallel: ‘1’ indicates request pending.
Rxbusy
ExtM
Bit 6
Bit 6
Section 7.1.5 on page
Section 7.1.6 on page
X
6
Rxunfair
Bit 5
Bit 5
ExtT
X
5
109, the description of the MICR, for details on the RICR.
110, the description of the MIR, for details on the RIR.
ExtR
Bit 4
Bit 4
X
4
1
Description
Bit 3
SRP
Bit 3
C1
3
1
Bit 2
SRM
Bit 2
C0
2
0
ch[1]
Bit 1
Bit 1
SRT
8-Bit Hex Address: 44
8-Bit Hex Address: 6B
8-Bit Hex Address: 67
X
1
Chapter 5.0
Default Value: 18
Default Value: 00
Default Value: 00
Datasheet
ch[0]
Bit 0
Bit 0
SRR
for a
0
X
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