SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 122

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.3.2
122
Register Name: CCSR
Register Description: Channel Control Status
Access: Read only
RxEN
Bit 7
Bit
7:5
3:0
Bit
4
7
6
5
4
3
Channel Control Status Register
The CCSR provides current receiver/transmitter status of the selected channel.
Description
Must be ‘0’.
Must be ‘1’.
Select channel enable/disable activity:
Receiver Enabled: This bit is set when the receiver is enabled and cleared when it is disabled.
Receiver Flow Off: This bit indicates that the receiver has requested the remote to stop transmitting through
the use of a send XOFF character by a send special character 2 command in the CCR. The bit is cleared
when a send special character 1 (XON) command is issued; the channel is either enabled or disabled, or the
channel is reset.
Receiver Flow On: When a send special character 1 (XON) command is issued by the CCR, this bit is set.
This bit is cleared when one of three events has occurred, 1) the first non-flow control character is received,
2) the receiver is either enabled or disabled, 3) or the channel is reset.
Reserved: This bit returns ‘0’ when read.
Transmitter Enabled: This bit is set when the transmitter is enabled and cleared when it is disabled.
RxFloff
Bit 6
XMT EN
0
0
0
1
0
0
1
1
RxFlon
XMT DIS
Bit 5
0
0
1
0
1
1
0
0
RCV EN
Bit 4
0
1
0
0
0
1
0
1
0
RCV DIS
Description
1
0
0
0
0
0
1
0
TxEN
Bit 3
Disable receiver.
Enable receiver.
Disable transmitter.
Enable transmitter.
Disable transmitter and receiver.
Disable transmitter; enable receiver.
Enable transmitter; disable receiver.
Enable transmitter and receiver.
TxFloff
Bit 2
Encoding
TxFlon
Bit 1
8-Bit Hex Address: 0B
Default Value: 00
Datasheet
Bit 0
0