SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 38

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
38
ADDRESS
CONTROL
CPU I/O
CPU
Figure 5. Control Signal Generation
Table 14. Request-Type Bit Assignments
Bit 2
0
0
0
0
1
1
1
1
For transmit and modem service-acknowledge cycles, the data in the lower three bits is redundant
to the software because the corresponding acknowledge has occurred. These bits are important in
the case of a serial receive-data service acknowledge because they provide an indication of whether
the request is for ‘good’ data or exception data. They are important to the parallel port because they
indicate if the state-machine or data pipeline (or both) are requesting service.
The value contained in the upper five bits of the LIVR can be used for a number of purposes. The
primary purpose of the LIVR is as a source of a software vector used by the system as an index into
a interrupt dispatch table. However, systems that cannot use this or do not need it can use these bits
for any purpose. In multiple–CD1284 designs that use daisy-chaining, a logical value to place in
these bits is a chip identification number. This is detailed in the daisy-chaining description in
Section
Bit 1
0
0
1
1
0
0
1
1
5.3.4.
ADDRESS
DECODE
LOGIC
Bit 0
0
1
0
1
0
1
0
1
Not used
Group 1: Modem signal change service request
Group 2: Transmit data service request
Group 3: Received good data service request
Parallel port state-machine requests service (refer to
Parallel port data pipeline request service (refer to
Both the parallel port state-machine and data pipeline request service (refer to
Section
Group 3: Received exception data service request
5.4)
Request Type
CS*
SVCACKR*
SVCACKT*
SVCACKM*
SVCACKP*
DGRANT*
R/W*
DS*
AD[6:0]
CD1284
DB[7:0]
Section
Section
5.4)
5.4)
Datasheet
DATA
CPU