SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 83

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

5.13.5
5.14
5.15
Datasheet
Table 21. System Clock Settings
The handshake is identical for both ECP and RLE modes. The control signals, HstBsy and PerBsy
(in the forward and reverse directions, respectively), indicate command and address options. If
HstBsy/PerBsy is low, the upper bit of the byte is examined: ‘0’ indicates to interpret the lower 7
bits as an address; ‘1’ indicates to use the lower 7 bits as an RLE repeat count. This count shows
the number of times to consecutively repeat that the next data character in the datastream.
The master device is responsible for determining the direction of the transfer. The slave can request
a direction change, but the master actually changes the direction. ECP mode always begins in the
forward direction, from master to slave. The CPU sets the RevRq bit (SCR[0]) to request reverse
transfers. Once the master changes direction, RevRq is automatically cleared and the DirCh
interrupt status appears in PCISR (if enabled in the PCIER).
The master device switches the direction of the interface for forward transfers when the slave
indicates no more data is available.
EPP Mode
Data transfers use the DMA pipeline and the FIFO. Address transfers are handled out-of-band, not
in the FIFO stream. When the slave receives an address write command, it deposits the address into
the EAR and asserts an EPPAW interrupt request. When the slave receives a read address
command, the contents of the EAR are returned.
Protocol Timing
The IEEE-1284 specification timing parameter T
minimum setup time as 500 ns. The SPR must be loaded with the number of system clock ticks
equivalent to 500 ns.
General-Purpose I/O Port
The CD1284 provides an 8-bit general-purpose port (GP[7:0]) to control or give status of external
functions. Each of the eight signals is individually programmable for direction, so the port can be
comprised of any number of inputs and outputs. Each port signal is implemented with a standard,
bidirectional HCMOS pad and is fully TTL compatible. The port is controlled by two internal
registers – GPDIR and GPIO.
Each bit in the GPDIR sets the direction of the corresponding bit in the GPIO; ‘1’ sets the signal as
output; ‘0’ sets it as input. When writing to the GPIO, only the bits programmed as outputs are
affected by the contents of the data bus. When reading the GPIO, bits programmed as inputs reflect
the true state of the condition of the external pin; bits programmed as outputs reflect the state of the
last value written to the register and the current state of the output pins.
CLK Freq.
(MHz)
16
20
25
Time/Tick
(ns)
62.5
50
40
IEEE 1284-Compatible Parallel Interface Controller — CD1284
SPR Value
10
13
8
P
T
specifies the minimum pulse width and the
P
500
500
520
Width
83