SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 117

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

7.2.6
7.2.7
Datasheet
Register Name: TDR
Register Description: Transmit Data
Access: Write only
Register Name: TIVR
Register Description: Transmit Interrupt Vector
Access: Read only
Bit 7
Bit 7
X
Transmit Data Register
The transmit data register is the port for the host to write to the transmit FIFO. When a channel is
being serviced for a transmit service request, the host can write up to 12 characters to this register.
The transmit data register should only be written during the context of a transmit-service
acknowledge. A write of data to this location at any other time yields unpredictable results.
Transmit Interrupt Vector Register
The value in this register is placed on the data bus, DB[7:0], when SVCACKT* is activated in
response to an active SVCREQT*. See
Bit 6
Bit 6
X
IT2
IT2
0
1
1
1
0
0
0
1
1
l
l
Bit 5
Bit 5
IT1
IT1
X
1
0
1
1
0
0
1
1
1
l
l
IEEE 1284-Compatible Parallel Interface Controller — CD1284
IT0
Bit 4
IT0
Bit 4
1
0
0
1
Transmit Character
0
1
0
1
1
l
l
X
Section 7.4.6 on page 128
Group 3: Received good data service request.
Invalid.
Group 3: Received exception data service request.
No transmit interrupt active.
Invalid.
Group 2: Transmit data service request.
Invalid.
Bit 3
Bit 3
X
Bit 2
Bit 2
IT2
Description
Description
for more details on the LIVR.
Bit 1
Bit 1
IT1
8-Bit Hex Address: 63
8-Bit Hex Address: 42
Default Value: 00
Default Value: 00
Bit 0
Bit 0
IT0
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