SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 54

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
5.5.4
54
Transmitter Operation
Each of the two serial channels on the CD1284 are capable of transmitting characters with a
number of programmable characteristics such as length, parity, and baud rate. The channels operate
independently and the settings in one have no effect on the operation of the other.
After being reset from either hardware (RESET* input pin) or software (by the master reset
command in the CCR), all transmitters are disabled with the TxD output held at a logic ‘1’
condition. This is the ‘off’ or ‘mark’ condition of the asynchronous protocol.
Before any operation of the transmitter can begin, the CPU must program the appropriate
parameters in the CORs, TCOR, and TBPR. Once these registers are set, the channel is enabled by
issuing a transmit enable command through the CCR, and enabling service requests by setting the
appropriate transmit enable request bits in the SRER.
The channel then immediately posts a transmit service request since its FIFO is empty. The CPU
responds to the request by loading up to 12 characters into the transmit FIFO through the TDR after
it places the CD1284 in the Service-Request Acknowledge mode (see description of service-
request/service-acknowledge procedures in
The transmitter does not begin transmitting the characters until the CPU terminates the service
routine and writes the EOSRR. Transmission begins by sending a start bit (a logic ‘0’) followed by
five to eight data bits (depending on the programmed value), least-significant bit first. The last data
bit is followed by the appropriate parity bit, if enabled, and a minimum of one stop bit.
All bit transmission is handled by the transmit bit engine with the MPU sending each bit as
requested. If there are still characters in the FIFO, the next one is transmitted immediately after the
last stop bit of the previous character. This process continues until all characters in the FIFO are
transmitted. At that time the CD1284 posts a service request for more data.
There are actually 14 transmit character holding locations for each channel: 12 in the FIFO, one in
the Transmitter Holding register, and one in the Transmitter Shift register. The CD1284 can be
programmed on a per-channel basis to request transmit data when one of two conditions exist:
Option number one allows the CPU two character transmit times to reload the FIFO and prevent a
transmit data underrun. This is the normal mode of operation. Option number two ensures that the
transmitter is empty before reconfiguring the channel. It is likely that transmitter underrun occurs if
option number two is selected, unless the CPU is sufficiently fast to respond to a transmit service
request and reload the FIFO during transmission of the stop bit(s) of the last character.
If the transmitter underruns, it continues to send stop bits (mark) until more data is placed in the
FIFO. Normally, when a string of characters greater than 12 is being transmitted, the software
programs the CD1284 transmitter to post a service request when the FIFO is empty. When the last
of the data to send is placed in the FIFO, the service request enable is changed so that requests are
made after the last character is sent. This notifies the CPU that all the data was transmitted before
disabling a channel.
If a channel is disabled without first being emptied, any characters other than the one currently
being transmitted are held and the transmitter enters the marking state. If the channel is
subsequently reenabled, any remaining data is transmitted.
1. When the last character in the FIFO is transferred to the holding register, or
2. When the last data bit of the last character is shifted out of the Transmitter Shift register.
Section
5.2.3).
Datasheet