SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 137

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

7.7.2
7.7.3
Datasheet
7
6
5
4
3
2
1
0
Register Name: DMABUFH
Register Description: DMA Buffer Data Register, high
Access: Read/Write
Register Name: DMABUFL
Register Description: DMA Buffer Data Register, low
Access: Read/Write
Bit 7
Bit 7
15
7
Bit
DMA Buffer Data Register — High
DMA Buffer Data Register — Low
This 16-bit data register is used to buffer DMA data transfers to and from the CD1284. Under
normal operating conditions, this register is only accessed during a DMA data transfer cycle. If the
DMAbufWe (PFCR[0]) is set to ‘1’ and DMAdir (PFCR[5]) is set to ‘1’, data may be transferred
from the host to the FIFO by directly writing to the DMABUF. The data automatically moves
forward into the FIFO through the Data Pipeline Holding registers. The user must ensure that the
FIFO has sufficient free space to accept the data before writing into the DMABUF.
The BYTESWAP pin determines the order of byte transfer from this register into the data pipeline.
If BYTESWAP is set to ‘1’, data transferred on DB[15:8] is the first byte transferred into the data
pipeline and DB[7:0] is transferred second. If BYTESWAP is set to ‘0’ this sequence is reversed.
The same applies during data read during DMA transfers: if BYTESWAP is set to ‘1’, data from
the data pipeline moves to the upper byte of DMABUF, the next byte moves into the lower byte.
Again, if BYTESWAP is set to ‘0’, this sequence is reversed.
DMA Write Error: This bit is set if the DMA control logic has written to the DMA buffer when it already
contains data. It indicates that an invalid DMA transfer cycle occurred (a DMAACK* without a corresponding
DMAREQ*).
DMA Read Error: As with bit 7, this bit indicates that DMA logic has performed a read from the DMA buffer
when there was no data in it. It indicates that an invalid DMA transfer cycle occurred.
Buffer Write Error: This bit indicates that a system write to the DMA buffer occurred while it still contained
data.
Buffer Read Error: This bit indicates that a system read from the DMA buffer occurred while it was empty.
Holding Register 1 Write Error: This bit indicates that a system write to PFHR1 occurred while it still
contained data.
Holding Register 1 Read Error: This bit indicates that a system read from PFHR1 occurred while it was
empty.
Holding Register 2 Write Error: This bit indicates that a system write to PFHR2 occurred while it still
contained data.
Holding Register 2 Read Error: This bit indicates that a system read from PFHR2 occurred while it was
empty.
Bit 6
Bit 6
14
6
Bit 5
Bit 5
13
5
IEEE 1284-Compatible Parallel Interface Controller — CD1284
Bit 4
Bit 4
12
4
Description
Bit 3
Bit 3
11
3
Bit 2
Bit 2
10
2
Bit 1
Bit 1
8-Bit Hex Address: 30
8-Bit Hex Address: 30
9
1
Default Value: 00
Default Value: 00
Bit 0
Bit 0
8
0
137