SCD1284 INTEL [Intel Corporation], SCD1284 Datasheet - Page 80

• Manufacturer Part Number: SCD1284
• Description: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
• Manufacturer: INTEL [Intel Corporation]

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
5.12.8
5.12.9
80
DB[15:8]
DB[7:0]
Figure 12. FIFO Data Path Functional Diagram — Transmit
Parallel Port Interface to the FIFO
The DMAdir bit indicates the current direction (0 in; 1
the DMA logic. Due to a recent negotiation, this can differ from the current parallel-port interface
direction. The CPU must change the direction after it receives an interrupt showing a direction
change. The FIFOlock bit (PACR[4]) stops the DMA pipeline, useful in diagnostics.
1284 Negotiations
All IEEE STD 1284 protocol negotiations are initiated by the master side. The role of the CD1284
is to accept or reject the attempted negotiation. The NER contains bits to individually enable
specific IEEE 1284 modes.
The various IEEE 1284 modes require negotiations on the parallel interface before they can be
entered. Until a successful negotiation sequence is complete, the interface remains in Compatibility
mode. These negotiations occur in two stages; both stages occur automatically after the device is
commanded to begin the negotiation procedure to a particular mode. The first stage determines if
the slave is IEEE 1284-compatible. Once determined, the interface continues the process to
determine if the mode requested is supported. The result of the requested negotiation appears in the
NSR.
For negotiations to occur, the slave must enable the E1284 bit (PCR[6]). Data transfers require that
the ETxfr bit (PCR[5]) be set; negotiations can occur without data transfer enabled.
(TRANSMIT)
TAG BIT
PFCR
STATUS
TAG
STATUS
TAG
out) of transfers between the FIFO and
FIFO (64 BYTES)
TAG (64 BITS)
Datasheet