K9F4G08U0M SAMSUNG [Samsung semiconductor], K9F4G08U0M Datasheet - Page 16

• Manufacturer Part Number: K9F4G08U0M
• Description: 512M x 8 Bits / 1G x 8 Bits NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9K8G08U1M
K9F4G08U0M
NAND Flash Technical Notes
Copy-Back Operation with EDC & Plane Definition for EDC
Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source
page has a bit error for charge loss or charge gain, accumulated copy-back operations could also accumulate bit errors. For this rea-
son, two-bit ECC is recommanded for copy-back operation.
Because K9F4G08U0M supports Copy Back with EDC operation, only 1-bit ECC is sufficient for copy-back operation. During Copy-
Back operation, the system controller can detect a bit error for each 528-byte plane by monitoring the Status bits (I/O1 & I/O 2) of the
Status Register.
There are some restrictions against programming unit in copy-back operation with EDC. For enabling EDC operation, the page pro-
gram should be performed with the whole page unit (2,112-byte) or the each 528-byte plane unit. A page of 2,112-byte is composed
of 4 planes of 528-byte and each 528-byte plane is made up of 512-byte in the main area and 16-byte in the spare area.
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig-
nificant bit) pages of the block. Random page address programming is prohibited.
Table 2. Definition of the 528-Byte Plane
2’nd 528-Byte Plane
1’st 528-Byte Plane
3’rd 528-Byte Plane
4’th 528-Byte Plane
(1’st plane)
"A" area
512 Byte
Plane
Page 63
Page 31
Page 2
Page 1
Page 0
From the LSB page to MSB page
DATA IN: Data (1)
(2’nd plane)
512 Byte
"B" area
Area Name
Data register
Main Area (2,048 Byte)
"A"
"B"
"C"
"D"
(64)
(32)
Main Area (Column 0~2,047)
(3)
(2)
(1)
:
:
(Continued)
Data (64)
(3’rd plane)
"C" area
512 Byte
Column Address
1,024 ~ 1,535
1,536 ~ 2,047
512 ~ 1,023
0 ~ 511
16
(4’th plane)
"D" area
512 Byte
Page 63
Page 31
Page 2
Page 1
Page 0
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Area Name
Spare Area (Column 2,048~2,111)
(1’st plane)
"G"
"E"
"F"
"H"
"E" area
16 Byte
Data register
FLASH MEMORY
Spare Area (64 Byte)
(2’nd plane)
(64)
(32)
(1)
(3)
(2)
"F" area
16 Byte
:
:
Column Address
Data (64)
2,048 ~ 2,063
2,064 ~ 2,079
2,080 ~ 2,095
2,096 ~ 2,111
(3’rd plane)
"G" area
16 Byte
Advance
(4’th plane)
"H" area
16 Byte