K9F4G08U0M SAMSUNG [Samsung semiconductor], K9F4G08U0M Datasheet - Page 38

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K9F4G08U0M

Manufacturer Part Number
K9F4G08U0M
Description
512M x 8 Bits / 1G x 8 Bits NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet

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K9K8G08U1M
K9F4G08U0M
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to Table 3 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table 3. Staus Register Definition for 70h Command
NOTE :
Table 4. Status Register Definition for 7Bh Command
NOTE :
READ EDC STATUS
Read EDC status operation is only available on ’Copy Back Program’. The device contains a EDC Status Register which may be
read to find out whether there is error during ’Read for Copy Back’. After writing 7Bh command to the command register, a read cycle
outputs the content of the EDC Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line
control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired.
RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command reg-
ister remains in EDC Status Read mode until further commands are issued to it.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7 Write Protect of Copy Back Program
I/O
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
I/O
2. More than 2-bit error detection isn’t available for each 528B plane.
Ready/Busy of Copy Back Program
Pass/Fail of Copy Back Program
That is to say, only 1-bit error detection is avaliable for each 528B plane.
Validity of EDC Status
Copy Back Program
EDC Status
Page Program
Not Use
Not Use
Not Use
Write Protect
Ready/Busy
Pass/Fail
Not Use
Not Use
Not Use
Not use
Not use
Block Erase
Write Protect
Ready/Busy
Page Program
Pass/Fail
Write Protect
Ready/Busy
Not Use
Not Use
Not Use
Not use
Not use
Pass/Fail
Not Use
Not Use
Not Use
Not use
Not use
Block Erase
Write Protect
Ready/Busy
38
Pass/Fail
Not Use
Not Use
Not Use
Not use
Not use
Write Protect
Ready/Busy
Not Use
Not Use
Not Use
Not use
Not use
Not use
Read
Write Protect Protected : "0", Not Protected :"1"
Ready/Busy
Not Use
Not Use
Not Use
Not use
Not use
Not use
Read
Pass : "0"
Don’t -cared
Don’t -cared
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
Protected : "0"
Pass : "0", Fail : "1"
No Error : "0", Error : "1"
Valid : "1", Invalid : "0"
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0", Ready : "1"
FLASH MEMORY
Definition
Definition
Not Protected : "1"
Ready : "1"
Fail : "1"
Advance

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