EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 12

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A11 (input pins)
Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A7 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This
column address becomes the starting address of a burst operation.
[Address Pins Table]
Part number
EDD1232ACBH
A8 (AP) (input pin)
A8 defines the precharge mode when a precharge command, a read command or a write command is issued. If A8
= high when a precharge command is issued, all banks are precharged. If A8 = Low when a precharge command is
issued, only the bank that is selected by BA1/BA0 is precharged. If A8 = high when read or write command, auto-
precharge function is enabled. While A8 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
Bank 0
Bank 1
Bank 2
Bank 3
Remark: H: VIH. L: VIL.
Data Sheet E1202E20 (Ver.2.0)
Address (A0 to A11)
Row address
AX0 to AX11
BA0
L
H
L
H
12
Column address
AY0 to AY7
BA1
L
L
H
H
EDD1232ACBH