EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 24

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Read/Write Operations
Bank active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCDRD or
tRCDWR after the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select
address which are loaded via the A0 to A11 and BA0, BA1 pins in the cycle when the read command is issued. The
data output timing are characterized by CL and tAC. The read burst start CL
edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously
with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low
period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling
edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.
tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is
referred as read postamble.
Command
Data Sheet E1202E20 (Ver.2.0)
DQS
DQ
Address
/CK
CK
NOP
t0
Row
ACT
t1
BL = 2
BL = 4
BL = 8
tRCDRD
NOP
Read Operation (Burst Length)
Column
READ
t5
t6
24
t7
tRPRE
NOP
t8
out0 out1
out0 out1 out2 out3
out0 out1 out2 out3 out4 out5 out6 out7
tCK + tAC (ns) after the clock rising
t9
tRPST
EDD1232ACBH
t10
CL = 3
BL: Burst length
t11