EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 13

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is high, the next CK rising edge is valid. If CKE is
Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered
when the CKE is driven Low and exited when it resumes to high. CKE must be maintained high throughout read or
write access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
DM0 to DM3 (input pin)
DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS and VREF.
When DM = high, the data input at the same timing are masked while the internal burst counter will be counting up.
Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
DQ0 to DQ31 (input/output pins)
Data is input to and output from these pins.
DQS0 to DQS3 (input and output pin): DQS0 to DQS3 provide the read data strobes (as output) and the write
data strobes (as input).
Correspondence Table).
[DQS and DM Correspondence Table]
DQS
DQS0
DQS1
DQS2
DQS3
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E1202E20 (Ver.2.0)
Data mask
DM0
DM1
DM2
DM3
Each DQS pin corresponds to eight DQ pins, respectively (See DQS and DM
13
DQs
DQ0 to DQ7
DQ8 to DQ15
DQ16 to DQ23
DQ24 to DQ31
EDD1232ACBH