EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 8

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Parameter
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command period
Auto refresh to Active/Auto refresh command
period
Active to Read delay
Active to Write delay
Precharge to active command period
Active to Auto precharge delay
Active to active command period
Write recovery time
Auto precharge write recovery and precharge
time
Internal write to Read command delay
Average periodic refresh interval
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
Data Sheet E1202E20 (Ver.2.0)
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
12. VDD is assumed to be 2.5V 0.125V/+0.2V. VDD power supply variation per cycle expected to be less
definitions, see ‘Timing Waveforms’ section.
transition is defined to occur when the signal level crossing VTT.
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
reference voltage to judge this transition is not given.
assured.
values are 10% of tCK.
than 0.4V/400 cycle.
Symbol
tMRD
tRAS
tRC
tRFC
tRCDRD
tRCDWR
tRP
tRAP
tRRD
tWR
tDAL
tWTR
tREFI
-5B
2
40
55
60
15
10
15
tRCDRD min.
10
15
RU (tWR/tCK) +
RU (tRP/tCK)
2
—
min.
8
120000
max.
—
—
—
—
—
—
—
—
—
—
—
7.8
EDD1232ACBH
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
µs
Notes