EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 40

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Refresh Requirements
The 128M (X32) DDR SDRAM requires a refresh of all rows in any rolling 32ms interval. Each refresh is generated
in one of two ways by an explicit automatic refresh command, or by an internally timed event in self-refresh mode.
Dividing the number of device rows into the rolling 32ms interval defines the average refresh interval, tREFI, which is
a guideline to controllers for distributed refresh timing.
Auto-Refresh
When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the automatic
refresh mode (REF). All banks of the 128M (X32) DDR SDRAM must be precharged and idle for a minimum of the
precharge time (tRP) before the auto refresh command (REF) can be applied. An address counter, internal to the
device, supplies the bank address during the refresh cycle. No control of the external address bus is required once
this cycle has started.
When the refresh cycle has completed, all banks will be in the precharged (idle) state. A delay between the auto
refresh command (REF) and the next activate command or subsequent auto refresh command must be greater than
or equal to the auto refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of 8 refresh commands can be posted to any given DDR SDRAM, meaning that the
maximum absolute interval between any refresh command and the next Refresh command is 9
Burst refreshing or posting by the DRAM controller greater than 8 refresh cycles is not allowed.
Data Sheet E1202E20 (Ver.2.0)
Command
CKE
/CK
CK
t0
VIH
PRE
t1
≥ tRP
NOP
t2
t3
REF
Auto-Refresh
≥ tRFC
40
REF
≥ tRFC
EDD1232ACBH
NOP
tREFI.
Command
Any