EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 28

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Command Intervals
A Read Command to the Consecutive Read Command Interval
1. Same
2. Same
3. Different
Data Sheet E1202E20 (Ver.2.0)
Command
Destination row of the
consecutive read command
Bank
address
Address
DQS
/CK
DQ
CK
BA
Bank0
Active
Row address State
Same
Different
Any
ACT
Row
t0
READ to READ Command Interval (same ROW address in the same bank)
NOP
ACTIVE
—
ACTIVE
IDLE
Column A
READ
t4
Operation
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank to interrupt the preceding read operation. tRP after the
precharge command, issue the ACT command. tRCDRD after the ACT command,
the consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
The consecutive read can be performed after an interval of no less than 1 cycle to
interrupt the preceding read operation.
Precharge the bank without interrupting the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCDRD after the ACT
command, the consecutive read command can be issued.
Column = A
Read
Column B
READ
t5
Column = B
Read
28
t6
t7
Column = A
Dout
out
A0
out
A1
NOP
t8
out
B0
Column = B
Dout
out
B1
t9
out
B2
EDD1232ACBH
out
B3
t10
CL = 3
BL = 4
Bank0
t11