EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 25

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst write is defined
by the column address, the bank select address which are loaded via the A0 to A11, BA0 to BA1 pins in the cycle
when the write command is issued. DQS should be input as the strobe for the input-data and DM as well during
burst operation. tWPREH prior to the first rising edge of the DQS should be set to Low and tWPST after the last
falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble.
The last low period of DQS is referred as write postamble.
Data Sheet E1202E20 (Ver.2.0)
Command
DQS
DQ
Address
/CK
CL = 3
CK
Command
NOP
DQS
/CK
t0
DQ
CK
Row
ACT
READ
t1
BL = 2
BL = 4
BL = 8
t0
tRCDWR
NOP
t0.5
Read Operation (/CAS Latency)
t1
tWPRES
WRITE
Column
t4
t1.5
tRPRE
Write Operation
tWPREH
t4.5 t5
tAC,tDQSCK
t2
in0
in0
in0
25
t2.5
in1
in1
in1
NOP
in2
in2
t6
t3
out0
in3
in3
tWPST
t3.5
in4 in5
t7
out1
t4
NOP
out2
t4.5
in6
t8
out3
in7
EDD1232ACBH
t5
tRPST
t9
t5.5
BL: Burst length
VTT
VTT