EDD1232ACBH ELPIDA [Elpida Memory], EDD1232ACBH Datasheet - Page 41

• Manufacturer Part Number: EDD1232ACBH
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Self-Refresh
The self-refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered
down. When in the self-refresh mode, the DDR SDRAM retains data without external clocking. The self-refresh
command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled
upon entering self-refresh, and is automatically enabled upon exiting self-refresh. Any time the DLL is enabled a
DLL reset must follow and 200 clock cycles should occur before a read command can be issued. Input signals
except CKE are “Don’t care” during self-refresh. Since CKE is an SSTL2 input, VREF must be maintained during
self-refresh.
The procedure for exiting self-refresh requires a sequence of commands. First, CK must be stable prior to CKE
going back high. Once CKE is high, the DDR SDRAM must have NOP commands issued for tSNR because time is
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before applying any other command.
The use of self-refresh mode introduces the possibility that an internally timed event can be missed when CKE is
raised for exit from self-refresh mode. Upon exit from self-refresh an extra auto-refresh command is recommended.
Data Sheet E1202E20 (Ver.2.0)
Command
CKE
/CK
CK
t0
Notes: 1. Device must be in the “All banks idle” state prior to entering self-refresh mode.
tCH tCL
tCK
2. tSRD is applied for a read or a read with autoprecharge command.
3. tSNR is applied for any command except a read or a read with autoprecharge command.
t1
t2
t3
tRP*
t4
1
Self-Refresh
tIS tIH
tIS
SELF
41
t5
t6
tIS
tm
NOP
≥ tSNR*
NOP
≥ tSRD*
EDD1232ACBH
3
2
NOP
Valid
tn