K9F5608Q0C-H SAMSUNG [Samsung semiconductor], K9F5608Q0C-H Datasheet - Page 29

• Manufacturer Part Number: K9F5608Q0C-H
• Description: 32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data
within the selected page are transferred to the data registers in less than 10 s(t
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in
50ns(K9F5616Q0C : 60ns) cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from
the selected column address up to the last column address.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Addresses A
device) or A
A
typical sequence and timings for each read operation.
Sequential Row Read is available only on
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10 s
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.
Figure8. Read1 Operation
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
K9F5608Q0C
K9F5608D0C
K9F5608U0C
CLE
CE
WE
ALE
R/B
RE
I/Ox
3~
A
7
must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the main area. Figures 8,9 show
array (00h) at next cycle.
0~
A
2
(X16 device) set the starting address of the spare area while addresses A
00h
X16 device : A
X8 device : A
Start Add.(3Cycle)
K9F5616Q0C
K9F5616D0C
K9F5616U0C
0
0
~ A
~ A
7
7
& A
& A
01h command is only available on X8 device(K9F5608X0C).
9
9
~ A
~ A
K9F5608U0C_Y,P,V,F or K9F5608D0C_Y,P
24
24
t
R
(00h Command)
Data Field
Main array
On K9F5608U0C_Y,P,V,F or K9F5608D0C_Y,P
CE must be held
low during tR
29
Spare Field
R
). The system controller can detect the completion of
:
Data Output(Sequential)
1)
4
1st half array
~A
7
are ignored in X8 device case or
FLASH MEMORY
(01h Command)
Data Field
2st half array
Spare Field
0~
A
3
(X8