HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 15

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

(1-5) 4 line type serial interface
(1-6) 3 line type serial interface
state should be released (CS = “H”) after 8bit data transfer as shown in the following figure.
D
clock.
serial clock (SCL) and state of command data bit polarity shift pin (SPOL).
CS
RS
SDA
SCL
of D
TABLE
TABLE
7
4 line serial interface by SDA and SCL is possible at chip selection state (CS=”L”)
When chip is not selected, internal shift register and counter are reset to initial value.
3-line serial interface by SDA and SCL is possible at chip selection state (CS=”L”)
When chip is not selected, internal shift register and counter are reset to initial value.
Input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence of RS,
Serial data (SDA) are identified to display data or command by RS bit data at the rising of first
Serial input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence
Serial data (SDA) are identified to display data or command by RS input.
Make serial clock (SCL) “L” at the non-access period and after 8bit data transfer.
SDA and SCL signals are sensitive to external noise. To prevent mal-function, chip selector
, ,D
7
,
RS
H
L
RS
H
L
, D
1
, D
1
, D
0
, and converted to 8bit parallel data and handled at the rising edge of 9th serial
0
D
1
and converted into 8-bit parallel data at the rising edge of 8th serial clock.
7
SPOL=L
Data contents
Display data
Data identify
Display data
command
command
D
2
6
D
3
5
4 line serial interface
D
4
4
D
5
RS
H
3
L
D
6
2
SPOL=H
D
7
1
Data identify
Display data
command
D
8
HM17CM256
VALID
0
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