HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 72

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

HM17CM256
- 72 -
(34-24) Internal register data read
(34-25) Window end X address set
(34-26) Window end Y address set
(34-23) Set read address of internal register
* : “Don’t care”
the address for internal register to read should be set first.
( reset :{RA
( reset :{EX
( reset :{EX
( reset :{EY
( reset :{EY
CS
CS
CS
CS
CS
CS
0
0
This command is used to read out internal register data.
0
0
0
0
first. For example, when display control (1) is being read out, { RA
specified first.
register.
by this command.
this command.
Before executing the internal register data read command the address of register should be specified
Because selected register is corresponded with RE flag, please set RE flag first and then read out the
Refer to the command function description and the lists of commands for the address of each register.
When the window area of RAM is specified(WIN=“1”) to access, the end X address of the window is set
When window area of RAM is specified(WIN=“1”) to access , the end Y address of the window is set by
RS
RS
RS
RS
RS
RS
1
1
1
1
1
1
3
6
3
6
3
~EX
~EX
~EY
~EY
, RA
RD
RD
RD
RD
RD
RD
1
1
1
1
1
1
0
4
0
4
2
}=0
}=0
}=0
}=0
, RA
H
H
H
H
WR
WR
WR
WR
WR
WR
, read address :0
, read address :1
, read address :2
, read address :3
1
0
0
0
0
0
0
, RA
The lower 4 bits of address should be set first and then upper 3 bits are set later.
The lower 4 bits of address should be set first and then upper 3 bits are set later
0
RE
RE
RE
RE
RE
RE
}=B
0/1
1
1
1
1
1
2
2
2
2
2
2
H
)
RE
RE
RE
RE
RE
RE
0/1
0
0
0
0
0
1
1
1
1
1
1
H
H
H
H
)
) * : “Don’t care”
)
) * : “Don’t care”
RE
RE
RE
RE
RE
RE
0/1
0
1
1
1
1
0
0
0
0
0
0
D
D
D
D
D
D
1
0
0
0
0
*
7
7
7
7
7
7
D
D
D
D
D
D
1
0
0
0
0
*
6
6
6
6
6
6
Before executing this command, RE flag and
D
D
D
D
D
D
0
0
0
1
1
*
5
5
5
5
5
5
3
D
D
D
D
D
D
, RA
0
0
1
0
1
*
4
4
4
4
4
4
2
, RA
RA
EX
EY
Internal register data read
D
D
D
D
D
D
*
*
3
3
3
3
3
3
3
3
3
1
, RA
RA
EX
EX
EY
EY
D
D
D
D
D
D
2
2
2
2
2
2
2
2
6
2
6
0
} = 8
RA
EX
EX
EY
EY
D
D
D
D
D
D
1
1
1
1
1
1
1
H
1
5
1
5
should be
RA
EX
EX
EY
EY
D
D
D
D
D
D
0
0
0
0
0
0
0
4
0
0
4