HM17CM256 HYNIX [Hynix Semiconductor], HM17CM256 Datasheet - Page 54

• Manufacturer Part Number: HM17CM256
• Description: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: HYNIX [Hynix Semiconductor]

HM17CM256
(34) INSTRUCTION DESCRIPTION
- 54 -
(34-1) Write display data on RAM
(34-2) Read display data from RAM
(34-3) X address register set
(34-4) Y address register set
The left side of the following command code and data table are the setting of 80 series CPU`
interface.
As shown in instruction table, HM17CM256 has abundant command set
All the data code and command code are valid only when the chip select signal CS is at “0” state.
Writing the 8-bit display RAM data at specified X, Y address.
Reading out the 8-bit display RAM data from specified X, Y address.
One Dummy read cycle is needed after X, Y address is set.
( reset :AX
( reset :AX
Setting the X direction address address set. The lower 4-bits are set first, and then upper 3-bits are set later.
Please set from lower bit.
( reset :AY
( reset :AY
CS
CS
CS
CS
CS
CS
0
0
0
0
0
0
Please set from lower bit.
50
Setting the Y address of display RAM. The lower 4-bits are set first, and then upper 3-bits are set later.
00
H
,51
H
RS
RS
RS
RS
RS
RS
~51
0
0
1
1
1
1
H
3
6
3
6
is used for ICON display data address.
~AY
~AY
~AX
~AX
Do not use undefined command code.
H
is valid range at Y address(AY
RD
RD
RD
RD
RD
RD
0
4
4
4
1
0
1
1
1
1
=0
=0
=0
=0
H
H
H
H
, read address :2
, read address :3
, read address :0
, read address :1
WR
WR
WR
WR
WR
WR
0
1
0
0
0
0
RE
RE
RE
RE
RE
RE
0/1
0/1
0
0
0
0
2
2
2
2
2
2
RE
RE
RE
RE
RE
RE
0/1
0/1
0
0
0
0
H
1
1
1
1
1
1
) * : “Don’t care”
H
H
H
)
)
) * : “Don’t care”
RE
RE
RE
RE
RE
RE
0/1
0/1
0
0
0
0
6
~AY
0
0
0
0
0
0
0
). Do not use 52
D
D
D
D
D
D
0
0
0
0
7
7
7
7
7
7
D
D
D
D
D
D
0
0
0
0
6
6
6
6
6
6
H
~FF
D
D
D
D
D
Display RAM write data
D
Display RAM read data
0
0
1
1
5
5
5
5
5
5
H
range. The Y address(AY
D
D
D
D
D
D
0
1
0
1
4
4
4
4
4
4
.
AX
AY
D
D
D
D
D
D
*
*
3
3
3
3
3
3
3
3
AX
AX
AY
AY
D
D
D
D
D
D
2
2
2
2
2
2
2
6
2
6
AX
AX
AY
AY
D
D
D
D
D
D
1
1
1
1
1
1
1
5
1
5
6
~AY
AX
AX
AY
AY
D
D
D
D
D
D
0
0
0
0
0
0
0
0
4
) of
0
4