DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 10

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DM9000_09

Manufacturer Part Number
DM9000_09
Description
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Manufacturer
DAVICOM [Davicom Semiconductor, Inc.]
Datasheet
5.8 Power Pins
Final
Version: DM9000-DS-F03
April 23, 2009
68,69,70,
24,74,75,
55,72,90,
15,23,42,
58,63,81,
5,20,36,
99,76
71
78
79
80
77
73
PW_RST#
WAKEUP
GPIO0~3
LINK_O
DGND
DVDD
NC
I/O
O
O
P
P
I
General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GPIO1~3 defaults are input ports
Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
Power on Reset
Active low signal to initiate the DM9000
The DM9000 is ready after 5us when this pin deasserted
Not Connect
Digital VDD
Digital GND
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
DM9000
10

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