DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 28

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Final
Version: DM9000-DS-F03
April 23, 2009
16.15
16.14
16.13
16.12
16.10
16.11
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
6.1
6.0
Bit
LP_AN_ABLE
RPDCTR-EN
F_LINK_100
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BP_ADPOK
BP_ALIGN
PAGE_RX
Bit Name
BP_4B5B
BP_SCR
SMRST
MFPSC
TX
0, RO/LH
Default
0, RW
0, RW
0, RW
0, RW
0, RW
1, RW
0, RW
0, RW
0, RO
0, RO
1, RO
0, RO
0, RO
0, RO
0, RO
NP_ABLE = 1: next page available
NP_ABLE = 0: no next page
New Page Received
A new link of code-word page received. This bit will be
automatically cleared when the register (register 6) is read by
management
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports
Auto-negotiation
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5ccccccccB and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
Bypass ADPOK
Reserved
Write as 0, ignore on read
100BASE-TX
1 = 100BASE-TX operation
0 = Reserved
Reserved
Reserved
Write as 0, ignore on read
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Write as 0, ignore on read
Reserved
Write as 0, ignore on read
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0: Disable automatic reduced power down
1: Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Description
DM9000
28