DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 20

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.30 Memory data write command with address increment Register (F8H)
6.31 Memory data write_address Register (FAH~FBH)
6.32 TX Packet Length Register (FCH~FDH)
6.33 Interrupt Status Register (FEH)
6.34 Interrupt Mask Register (FFH)
Final
Version: DM9000-DS-F03
April 23, 2009
5~4
6~4
7:6
Bit
Bit
7:0
7:0
7:0
7:0
7:0
Bit
Bit
Bit
3
2
1
0
7
3
2
1
0
RESERVED
RESERVED
MWCMD
IOMODE
MDRAH
MDRAL
TXPLH
TXPLL
ROOM
Name
Name
Name
ROOS
Name
Name
ROM
ROS
PRM
PRS
PAR
PTM
PTS
00H,R/W
00H,R/W
0,RW/C1
0,RW/C1
0,RW/C1
0,RW/C1
Default
Default
Default
X,,R/W
X,R/W
Default
Default
X,WO
0, RO
0,RW
0,RW
0,RW
0,RW
0,RW
0,RO
0,RO
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1,2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
Memory Data Write_ address High Byte
Memory Data Write_ address Low Byte
TX Packet Length High byte
TX Packet Length Low byte
Bit 7 Bit 6
Reserved
Packet Transmitted Latch
Packet Received Latch
Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When driver
sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Receive Overflow Counter Overflow Latch
Enable RX Overflow Latch
Enable Packet Transmitted Latch
Enable Packet Received Latch
Receive Overflow Counter Overflow Latch
Rx Overflow Latch
0
0
1
1
0
1
0
1
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
16-bit mode
32-bit mode
8-bit mode
Reserved
Description
Description
Description
Description
Description
DM9000
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