DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 18

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.17 Multicast Address Register ( 16H~1DH )
6.18 General purpose control Register ( 1EH )
6.19 General purpose Register ( 1FH )
6.20 TX SRAM Read Pointer Address Register (22H~23H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Final
Version: DM9000-DS-F03
April 23, 2009
7:4
3:0
Bit
7:0
7:0
7:0
7:0
Bit
Bit
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:4
3:1
Bit
Bit
0
RESERVED
GEP_CNTL
RESERVED
RWPAH
RWPAL
GEPIO3-1
TRPAH
TRPAL
Name
Name
Name
GEPIO0
Name
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
Name
0CH,RO
00H,RO
00H.RO
04H.RO
0001,RW
Default
Default
Default
Default
Default
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
0,RO
0,RW
1,RW
0,RO
Multicast Address Byte 7 (1DH)
Multicast Address Byte 6 (1CH)
Multicast Address Byte 5 (1BH)
Multicast Address Byte 4 (1AH)
Multicast Address Byte 3 (19H)
Multicast Address Byte 2 (18H)
Multicast Address Byte 1 (17H)
Multicast Address Byte 0 (16H)
Reserved
General Purpose Control
Define the input/output direction of General Purpose Register
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. GPIO0 default is output for POWER_DOWN function. Other defaults are
input
Reserved
General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is reflected to pin GEPIO3-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GEPIO3-1
The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively
General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is the output to pin GEPIO0
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from pin GEPIO0. GEPIO0 default output 1 to
POWER_DOWN Internal PHY. Driver needs to clear this POWER_DOWN signal
by writing “0” when it wants PHY to be active. This default value can be
programmed by EEPROM. Please refer to the EEPROM description
TX SRAM Read Pointer Address High Byte (23H)
TX SRAM Read Pointer Address Low Byte (22H)
RX SRAM Write Pointer Address Low Byte (24H)
RX SRAM Write Pointer Address High Byte (25H)
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Description
Description
Description
Description
Description
DM9000
18