DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 16

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.10 Flow Control Threshold Register ( 09H )
6.11 RX/TX Flow Control Register ( 0AH )
6.12 EEPROM & PHY Control Register ( 0BH )
Final
Version: DM9000-DS-F03
April 23, 2009
Bit
7:4
3:0
7:6
Bit
Bit
7
6
5
4
3
2
1
0
5
4
3
2
1
0
RESERVED
ERPRW
RXPCS
ERPRR
HWOT
TXPEN
LWOT
Name
BKPM
Name
BKPA
RXPS
EPOS
ERRE
TXPF
FLCE
Name
REEP
TXP0
WEP
3H, RW
8H, RW
Default
Default
Default
0,RW
0,RW
0,RW
0,RW
0,RW
0,R/C
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RO
0,RO
0,RO
TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any packet
comes and RX SRAM is over BPHW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW
RX Pause Packet Status, latch and read clearly
RX Pause Packet Current Status
Flow Control Enable
Set to enable the flow control mode (i.e. to disable TX function)
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space.
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM
size
(1 unit=1K bytes)
Reserved
Reload EEPROM. Driver needs to clear it up after the operation completes
Write EEPROM Enable
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Description
Description
Description
DM9000
16