MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 17

• Manufacturer Part Number: MT48H32M32LFB5-6 IT:B
• Manufacturer: Micron

Table 10: AC Functional Characteristics
Notes 1–5 apply to all parameters and conditions
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
Parameter
Last data-in to burst STOP command
READ/WRITE command to READ/WRITE command
Last data-in to new READ/WRITE command
CKE to clock disable or power-down entry mode
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
LOAD MODE REGISTER command to ACTIVE or REFRESH command
CKE to clock enable or power-down exit mode
Last data-in to PRECHARGE command
Data-out High-Z from PRECHARGE command
Notes:
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper opera-
3. In addition to meeting the transition rate specification, the clock and CKE must transit
4. Outputs measured for 1.8V at 0.9V with equivalent load:
5. AC timing tests have V
6. The clock frequency must remain constant (stable clock is defined as a signal cycling
7.
8. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
9. This device requires 8192 AUTO REFRESH cycles every 64ms (
tion over the full temperature range (0˚C ≤ T
≤ T
between V
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus
capacitive loading, termination, and programmed drive strength.
input transition time is longer than
V
within timing constraints specified for the clock ball) during access or precharge states
(READ, WRITE, including
the data rate.
t
reference to V
cesses to a particular row address may result in reduction of the product lifetime.
uted AUTO REFRESH command every 7.8125μs meets the refresh requirement and en-
sures that each row is refreshed. Alternatively, 8192 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (
Q
HZ defines the time at which the output achieves the open circuit condition, it is not a
IH,min
A
≤ +85˚C industrial temperature) is ensured.
and no longer at the V
IH
and V
Electrical Specifications – AC Operating Conditions
OH
20pF
or V
IL
(or between V
OL
IL
. The last valid data element will meet
and V
t
WR, and PRECHARGE commands). CKE may be used to reduce
17
CL = 3
CL = 2
IH
IH
/2 crossover point.
with timing referenced to V
IL
t
Tmax, then the timing is referenced at V
Micron Technology, Inc. reserves the right to change products or specifications without notice.
and V
Symbol
t
t
t
t
t
t
CKED
t
t
t
t
t
DQM
DWD
t
t
t
DQD
MRD
DQZ
ROH
CCD
DAL
BDL
CDL
DPL
PED
RDL
1Gb: x32 Mobile LPSDR SDRAM
IH
t
) in a monotonic manner.
A
RFC), once every 64ms.
≤ +70˚C standard temperature and –40˚C
-6
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
t
IH/2
REF). Providing a distrib-
© 2010 Micron Technology, Inc. All rights reserved.
-75
t
OH before going High-Z.
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
= crossover point. If the
Units
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
IL,max
Notes
15, 17
16, 17
16, 17
and
13
13
14
14
13
13
13
13
14
13