MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 39
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MT48H32M32LFB5-6 IT:B
Manufacturer Part Number
MT48H32M32LFB5-6 IT:B
Description
Manufacturer
Micron
Datasheet
1.MT48H32M32LFB5-6_ITB.pdf
(81 pages)
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CAS Latency
Figure 12: CAS Latency
Operating Mode
Write Burst Mode
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ start driving as a result of the clock edge
one cycle earlier (n + m - 1), and provided that the relevant access times are met, the
data is valid by clock edge n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ command is registered at T0 and
the latency is programmed to two clocks, the DQ start driving after T1 and the data is
valid by T2.
Reserved states should not be used as unknown operation or incompatibility with fu-
ture versions may result.
Command
Command
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use. Reserved states should not
be used because unknown operation or incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M[2:0] applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CL = 2
NOP
NOP
T1
T1
39
t LZ
t AC
CL = 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2
NOP
NOP
T2
t LZ
D
t OH
1Gb: x32 Mobile LPSDR SDRAM
OUT
t AC
Don’t Care
T3
NOP
T3
D
t OH
OUT
© 2010 Micron Technology, Inc. All rights reserved.
Undefined
Mode Register
T4
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