MT48H32M32LFB5-6 IT:B Micron, MT48H32M32LFB5-6 IT:B Datasheet - Page 35
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MT48H32M32LFB5-6 IT:B
Manufacturer Part Number
MT48H32M32LFB5-6 IT:B
Description
Manufacturer
Micron
Datasheet
1.MT48H32M32LFB5-6_ITB.pdf
(81 pages)
- Current page: 35 of 81
- Download datasheet (3Mb)
Command 1
Figure 10: Initialize and Load Mode Register
PDF: 09005aef8404b23d
y68m_mobile_lpsdr.pdf – Rev. D 1/11 EN
BA0, BA1
Address
DQM
CLK
CKE
A10
Power-up:
CLK stable
DQ
V
DD
and
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T = 100µs
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CMS
CKS
Notes:
NOP
T0
t
High-Z
t
CMH
CKH
t
CK
1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REG-
2. NOPs or DESELECTs must only be provided during
3. NOPs or DESELECTs must only be provided during
ISTER command.
Precharge
All banks
all banks
t
AS
PRE
T1
t AH
t
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Tn + 1
AR
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35
RFC
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To + 1
AR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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1Gb: x32 Mobile LPSDR SDRAM
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2
Load mode
t AS t AH
t
AS
register
BA0 = L,
BA1 = L
Code
Code
Tp + 1
LMR
t
t
t
RFC time.
MRD time.
AH
t
MRD
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Load extended
mode register
3
© 2010 Micron Technology, Inc. All rights reserved.
BA0 = L,
BA1 = H
Code
BA0 = L,
Code
BA1 = L
LMR
Tq + 1
t
Initialization
MRD
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Valid
Valid
Valid
Valid
Tr + 1
Don’t Care
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