C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 136

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
10.5.1. Internal XRAM Only
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the
device. Memory accesses to addresses beyond the populated space will wrap on 8 kB boundaries. As an
example, the addresses 0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip XRAM space.
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10.5.2. Split Mode without Bank Select
When bit EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
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10.5.3. Split Mode with Bank Select
When EMI0CF[3:2] are set to 10, the XRAM memory map is split into two areas, on-chip space and off-
chip space.
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10.5.4. External Only
When EMI0CF[3:2] are set to 11, all MOVX operations are directed to off-chip space. On-chip XRAM is not
visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the
internal XRAM size boundary.
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8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address
and R0 or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]
are driven, determined by R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven
during the off-chip transaction.
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.
Effective addresses above the internal XRAM size boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-
chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower
8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are
driven in “Bank Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip
or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven
(identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This
allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower
8-bits of the effective address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full
16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
Rev. 0.5