C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 30

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
1.2. Port Input/Output
Digital and analog resources are available through 57 I/O pins (C8051F960/2/4/6/8) or 34 I/O pins
(C8051F961/3/5/7/9). Port pins are organized as eight byte-wide ports. Port pins can be defined as digital
or analog I/O. Digital I/O pins can be assigned to one of the internal digital resources or used as general
purpose I/O (GPIO). Analog I/O pins are used by the internal analog resources. P7.0 can be used as GPIO
and is shared with the C2 Interface Data signal (C2D). See Section “34. C2 Interface” on page 486 for
more details.
The designer has complete control over which digital and analog functions are assigned to individual port
pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. See
Section “27. Port Input/Output” on page 351 for more information on the Crossbar.
For Port I/Os configured as push-pull outputs, current is sourced from the VIO, VIORF, or VBAT supply pin.
Port I/Os used for analog functions can operate up to the supply voltage. See Section “27. Port Input/Out-
put” on page 351 for more information on Port I/O operating modes and the electrical specifications chap-
ter for detailed electrical specifications.
30
Highest
Priority
Lowest
Priority
SYSCLK
Outputs
SMBus
UART
T0, T1
P0
P6
P7
SPI0
SPI1
PCA
CP0
CP1
(P6.0-P6.7)
(P7.0)
Figure 1.11. Port I/O Functional Block Diagram
2
4
2
4
7
2
8
8
1
P0MASK, P0MAT
P1MASK, P1MAT
Port Match
(ADC0, CP0, and CP1 inputs,
To Analog Peripherals
VREF, IREF0, AGND)
Rev. 0.5
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Registers
Priority
Digital
8
8
8
8
8
8
8
1
PnMDIN Registers
PnMDOUT,
To EMIF
Cells
Cells
Cells
Cells
Cells
Cells
Cells
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0
P1
P2
P3
P4
P5
P6
P7
External Interrupts
EX0 and EX1
To LCD
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
P5.0
P5.7
P6.0
P6.7
P7.0