C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 342

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
SFR Definition 26.4. LCD0MSCN: LCD0 Master Control
SFR Page = 0x2; SFR Address = 0xAB
342
Note 1: To same bias generator is shared by the DCDC Converter and LCD0.
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
DCBIASOE
LOWDRV
Reserved
Reserved
LCDRST
BIASEN
CLKOE
LCDEN
Name
R/W
7
0
BIASEN
Read = 0b. Must write 0b.
LCD0 Bias Enable.
LCD0 bias may be disabled when using a static LCD (single backplane), contrast
control mode 1 (Bypass Mode) is selected, and the VLCD/VIO Supply Comparator
is disabled (LCD0CF.5 = 1). It is required for all other modes.
0: LCD0 Bias is disabled.
1: LCD0 Bias is enabled
DCDC Converter Bias Output Enable. (Note 1)
0: The bias for the DCDC converter is gated off.
1: LCD0 provides the bias for the DCDC converter.
LCD Clock Output Enable.
0: The clock signal to the LCD0 module is gated off.
1: The SmaRTClock provides the undivided clock to the LCD0 Module.
Read = 0b. Must write 0b.
Charge Pump Reduced Drive Mode.
This bit should be set to 1 in Contrast Control Mode 3 and Mode 4 for minimum
power consumption. This bit may be set to 0 in these modes to support higher load
current requirements.
0: The charge pump operates at full power.
1: The charge pump operates at reduced power.
LCD0 Reset.
Writing a 1 to this bit will clear all the LCD0Dn registers to 0x00. This bit must be
cleared by software.
LCD0 Enable.
0: LCD0 is disabled.
1: LCD0 is enabled.
R/W
6
0
DCBIASOE
R/W
5
1
CLKOE
Rev. 0.5
R/W
4
0
Function
R/W
3
0
LOWDRV
R/W
2
0
LCDRST
R/W
1
0
LCDEN
R/W
0
0