C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 51

• Manufacturer Part Number: C8051F966-A-GQ
• Description: 8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F966-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
C1
C2
calculated based on a Fabrication Allowance of 0.05 mm.
the metal pad is to be 60  m minimum, all the way around the pad.
assure good solder paste release.
pad.
Components.
X1
e
Table 3.6. QFN-40 Landing Diagram Dimensions
5.80
5.80
0.15
Min
Figure 3.8. QFN-40 Landing Diagram
0.50 BSC
Max
5.90
5.90
0.25
Rev. 0.5
Dimension
X2
Y1
Y2
4.10
0.75
4.10
Min
C8051F96x
Max
4.20
0.85
4.20
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