LPC1114FHN33/302 NXP Semiconductors, LPC1114FHN33/302 Datasheet - Page 48

• Manufacturer Part Number: LPC1114FHN33/302
• Description: ARM Microcontrollers - MCU 32b 32K Flash 42I/O
• Manufacturer: NXP Semiconductors

Specifications of LPC1114FHN33/302

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1114
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, SSP, UART
• Maximum Operating Temperature: + 85 C
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Program Memory Type: Flash
• Factory Pack Quantity: 260
• Tradename: LPC1100L

NXP Semiconductors
LPC111X
Product data sheet
7.12.1 Features
7.14.1 Features
7.12 General purpose external event counter/timers
7.13 System tick timer
7.14 Watchdog timer (LPC1100 series, LPC111x/101/201/301)
The LPC1110/11/12/13/14/15 include two 32-bit counter/timers and two 16-bit
counter/timers. The counter/timer is designed to count cycles of the system derived clock.
It can optionally generate interrupts or perform other actions at specified timer values,
based on four match registers. Each counter/timer also includes up to two capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
Remark: The watchdog timer without windowed features is available on parts
LPC111x/101/201/301.
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
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Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
Up to two capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Internally resets chip if not periodically reloaded.
Debug mode.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 20 February 2013
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2013. All rights reserved.
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