LPC1113FHN33/303,5 NXP Semiconductors, LPC1113FHN33/303,5 Datasheet - Page 530

• Manufacturer Part Number: LPC1113FHN33/303,5
• Description: ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1113FHN33/303,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1113
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 24 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
14.7.2.3
14.7.2.4
14.7.2.5
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
15.1
15.2
15.3
15.4
15.5
15.5.1
15.6
15.7
15.7.1
15.7.2
15.7.3
15.7.4
15.7.5
15.7.5.1
15.7.6
15.7.7
15.7.7.1
15.7.7.2
15.7.8
15.7.9
15.7.10
15.8
15.8.1
15.8.2
15.8.3
15.8.4
15.9
15.9.1
15.9.2
15.9.3
15.9.4
15.9.5
15.9.6
15.9.7
15.9.8
15.9.9
15.9.10
15.10
15.10.1
15.10.2
UM10398
User manual
How to read this chapter . . . . . . . . . . . . . . . . 232
Basic configuration . . . . . . . . . . . . . . . . . . . . 232
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 232
General description . . . . . . . . . . . . . . . . . . . . 233
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 234
Register description . . . . . . . . . . . . . . . . . . . 234
I
I
Details of I
2
2
C operating modes . . . . . . . . . . . . . . . . . . . 242
C implementation and operation . . . . . . . . 245
SPI format with CPOL=0,CPHA=1 . . . . . . . . 227
SPI format with CPOL = 1,CPHA = 0 . . . . . . 227
SPI format with CPOL = 1,CPHA = 1 . . . . . . 229
I
I
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 235
I
237
I
I
0x4000 000C) . . . . . . . . . . . . . . . . . . . . . . . . 237
I
(I2C0SCLH - 0x4000 0010 and I2C0SCLL-
0x4000 0014) . . . . . . . . . . . . . . . . . . . . . . . . 238
Selecting the appropriate I
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
I
0x4000 0018) . . . . . . . . . . . . . . . . . . . . . . . . 239
I
- 0x4000 001C) . . . . . . . . . . . . . . . . . . . . . . . 239
Interrupt in Monitor mode . . . . . . . . . . . . . . . 240
Loss of arbitration in Monitor mode . . . . . . . 241
I
0x4000 00[20, 24, 28]) . . . . . . . . . . . . . . . . . 241
I
0x4000 002C) . . . . . . . . . . . . . . . . . . . . . . . . 241
I
0x4000 00[30, 34, 38, 3C]) . . . . . . . . . . . . . . 242
Master Transmitter mode . . . . . . . . . . . . . . . 242
Master Receiver mode . . . . . . . . . . . . . . . . . 243
Slave Receiver mode . . . . . . . . . . . . . . . . . . 244
Slave Transmitter mode . . . . . . . . . . . . . . . . 245
Input filters and output stages. . . . . . . . . . . . 246
Address Registers, ADDR0 to ADDR3 . . . . . 247
Address mask registers, MASK0 to MASK3. 247
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 247
Shift register, DAT. . . . . . . . . . . . . . . . . . . . . 247
Arbitration and synchronization logic . . . . . . 247
Serial clock generator . . . . . . . . . . . . . . . . . . 248
Timing and control . . . . . . . . . . . . . . . . . . . . 249
Control register, CONSET and CONCLR . . . 249
Status decoder and status register . . . . . . . . 249
Master Transmitter mode . . . . . . . . . . . . . . . 250
Master Receiver mode . . . . . . . . . . . . . . . . . 254
2
2
2
2
2
2
2
2
2
2
2
C Fast-mode Plus . . . . . . . . . . . . . . . . . . . 233
C Control Set register (I2C0CONSET -
C Status register (I2C0STAT - 0x4000 0004) . . .
C Data register (I2C0DAT - 0x4000 0008) . 237
C Slave Address register 0 (I2C0ADR0-
C SCL HIGH and LOW duty cycle registers
C Control Clear register (I2C0CONCLR -
C Monitor mode control register (I2C0MMCTRL
C Slave Address registers (I2C0ADR[1, 2, 3] -
C Data buffer register (I2C0DATA_BUFFER -
C Mask registers (I2C0MASK[0, 1, 2, 3] -
2
C operating modes. . . . . . . . . . . 249
2
C data rate and duty
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
14.7.3
14.7.3.1
15.10.3
15.10.4
15.10.5
15.10.5.1 STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . . 263
15.10.5.2 STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . . 263
15.10.6
15.10.6.1 Simultaneous Repeated START conditions from
15.10.6.2 Data transfer after loss of arbitration . . . . . . 265
15.10.6.3 Forced access to the I
15.10.6.4 I
15.10.6.5 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
15.10.7
15.10.8
15.10.9
15.10.10 The state service routines . . . . . . . . . . . . . . 267
15.10.11 Adapting state services to an application. . . 267
15.11
15.11.1
15.11.2
15.11.3
15.11.4
15.11.5
15.11.5.1 State: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 268
15.11.5.2 Master States . . . . . . . . . . . . . . . . . . . . . . . . 268
15.11.5.3 State: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 268
15.11.5.4 State: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15.11.6
15.11.6.1 State: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15.11.6.2 State: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15.11.6.3 State: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 269
15.11.6.4 State: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.11.6.5 State: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.11.7
15.11.7.1 State: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.11.7.2 State: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.11.7.3 State: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 270
15.11.7.4 State: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 271
15.11.8
15.11.8.1 State: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 271
15.11.8.2 State: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 271
15.11.8.3 State: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 271
15.11.8.4 State: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.11.8.5 State: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.11.8.6 State: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.11.8.7 State: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 272
15.11.8.8 State: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 273
15.11.8.9 State: 0xA0. . . . . . . . . . . . . . . . . . . . . . . . . . 273
15.11.9
15.11.9.1 State: 0xA8. . . . . . . . . . . . . . . . . . . . . . . . . . 273
15.11.9.2 State: 0xB0. . . . . . . . . . . . . . . . . . . . . . . . . . 273
Software example . . . . . . . . . . . . . . . . . . . . . 267
Semiconductor Microwire frame format . . . . 229
Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 231
Slave Receiver mode. . . . . . . . . . . . . . . . . . 257
Slave Transmitter mode . . . . . . . . . . . . . . . . 261
Miscellaneous states . . . . . . . . . . . . . . . . . . 263
Some special cases . . . . . . . . . . . . . . . . . . . 264
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 264
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
I
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 267
I
Initialization routine . . . . . . . . . . . . . . . . . . . 267
Start Master Transmit function . . . . . . . . . . . 267
Start Master Receive function . . . . . . . . . . . 268
I
Non mode specific states. . . . . . . . . . . . . . . 268
Master Transmitter states . . . . . . . . . . . . . . 269
Master Receive states . . . . . . . . . . . . . . . . . 270
Slave Receiver states . . . . . . . . . . . . . . . . . 271
Slave Transmitter states . . . . . . . . . . . . . . . 273
2
2
2
2
C-bus obstructed by a LOW level on SCL or
C state service routines . . . . . . . . . . . . . . . 266
C interrupt service . . . . . . . . . . . . . . . . . . . 267
C interrupt routine . . . . . . . . . . . . . . . . . . . 268
Chapter 29: Supplementary information
2
C-bus. . . . . . . . . . . . 265
UM10398
© NXP B.V. 2012. All rights reserved.
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