LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 212

• Manufacturer Part Number: LPC1111FHN33/102'5
• Description: ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1111FHN33/102'5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1111
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Program Memory Type: Flash
• Factory Pack Quantity: 4000

NXP Semiconductors
UM10398
User manual
13.5.17 UART RS485 Control register (U0RS485CTRL - 0x4000 804C)
Although
control, it is strongly suggested to let UART hardware implemented auto flow control
features take care of this, and limit the scope of TxEn to software flow control.
Table 201
Table 201. UART Transmit Enable Register (U0TER - address 0x4000 8030) bit description
The U0RS485CTRL register controls the configuration of the UART in RS-485/EIA-485
mode.
Table 202. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit
Bit
6:0
7
31:8 -
Bit
0
1
2
3
Symbol
-
TXEN
Symbol
NMMEN
RXDIS
AADEN
SEL
Table 201
describes how to use TXEN bit in order to achieve software flow control.
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When this bit is 1, as it is after a Reset, data written to the THR
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it detects that the a hardware-handshaking TX-permit
signal (CTS) has gone false, or with software handshaking,
when it receives an XOFF character (DC3). Software can set
this bit again when it detects that the TX-permit signal has gone
true, or when it receives an XON (DC1) character.
Reserved
Value
0
1
0
1
0
1
0
1
describes how to use TxEn bit in order to achieve hardware flow
Rev. 12 — 24 September 2012
Description
NMM enable.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is disabled.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
is enabled. In this mode, an address is detected
when a received byte causes the UART to set the
parity error and generate an interrupt.
Receiver enable.
The receiver is enabled.
The receiver is disabled.
AAD enable.
Auto Address Detect (AAD) is disabled.
Auto Address Detect (AAD) is enabled.
Select direction control pin
If direction control is enabled (bit DCTRL = 1), pin
RTS is used for direction control.
If direction control is enabled (bit DCTRL = 1), pin
DTR is used for direction control.
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
NA
1
-
Reset
value
0
0
0
0
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